May 04

Overview of Methodologies for the Thermal Measurement of Single- and Multi-Chip, Single- and Multi-PN-Junction Light-Emotting Diodes (LEDs)

JEDEC Solid State Technology Association / 18-Apr-2012 / 12 pages

This document provides an overview of the methodology necessary for making meaningful thermal measurements on high-power light-emitting diodes (LEDs) built on single or multiple chips with one or more pn-junctions per chip. The actual methodology components are contained in separate detailed documents.

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Mar 27

Serial Interface for Data Converters

JEDEC Solid State Technology Association / 01-Jan-2012 / 145 pages

This specification describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this specification. Informative annexes are included to clarify and exemplify the specification.

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Mar 06

REQUIREMENTS FOR HANDLING ELECTROSTATIC-DISCHARGE-SENSITIVE (ESDS) DEVICES

JEDEC Solid State Technology Association / 01-Jan-2012 / 31 pages

This standard establishes the minimum requirements for Electrostatic Discharge (ESD) control methods and materials used to protect electronic devices that are susceptible to damage or degradation from electrostatic discharge (ESD). The passage of a static charge through an electrostatic-discharge-sensitive (ESDS) device can result in catastrophic failure or performance degradation of the part.

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Nov 03

POD10 ? 1.0 V Pseudo Open Drain Interface

JEDEC Solid State Technology Association / 01-Sep-2011 / 16 pages

This document defines the 1.2 V Pseudo Open Drain Interface family of interface standards, POD12, which are generally expected to be implemented with differential amp-based input buffers that, when in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point.

Although this standard is named for the nominal value of VDDQ to be used, it is the input trip-point value that provides for inter operability of POD12 compliant devices.

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Oct 14

POD12-1.2 V Pseudo Open Drain Interface

JEDEC Solid State Technology Association / 01-Aug-2011 / 16 pages

This document defines the 1.2 V Pseudo Open Drain Interface family of interface standards, POD12, which are generally expected to be implemented with differential amp-based input buffers that, when in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point.

Although this standard is named for the nominal value of VDDQ to be used, it is the input trip-point value that provides for inter operability of POD12 compliant devices.

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Oct 12

Universal Flash Storage (UFS) Host Controller Interface

JEDEC Solid State Technology Association / 01-Aug-2011 / 58 pages

This standard describes a functional specification of the Host Controller Interface (HCI) for Universal Flash Storage (UFS). The objective of UFSHCI is to provide a uniform interface method of accessing the UFS hardware capabilities so that a standard/common Driver can be provided for the Host Controller. The common Driver would work with UFS host controller from any vendor.

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