Category Archives: JEDEC

JEDEC JS-001-2017

ESDA/JEDEC Joint Standard for Electrostatic Discharge Sensitivity Testing – Human Body Modal (HBM) – Component Level

Published by: 2017-05-12 / 2017-05-12
This standard establishes the procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD). The purpose (objective) of this standard is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels. NOTE Data previously generated with testers meeting all waveform criteria of ANSI/ESD STM5.1-2007 or JESD22A-114F shall be considered valid test data.

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JEDEC JESD22-B116B

WIRE BOND SHEAR TEST

Published by: 2017-04-01 / 2017-04-01 / 32 pages
This test provides a means for determining the strength of a gold ball bond to a die bonding surface or an aluminum wedge or stitch bond to a die or package bonding surface, and may be performed on pre-encapsulation or post-encapsulation parts. The wire bond shear test is destructive. It is appropriate for use in process development, process control and/or quality assurance.

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JEDEC JESD209-4B

Low Power Double Data Rate 4 (LPDDR4)

Published by: 2017-02-01 / 2017-02-01 / 307 pages
This document defines the LPDDR4 standard, including features, functionalities, AC and DC
characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the
minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or
two channels. LPDDR4 dual channel device density ranges from 4 Gb through 32 Gb and single channel
density ranges from 2 Gb through 16 Gb. This document was created using aspects of the following
standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2
(JESD209-2) and LPDDR3 (JESD209-3).

Each aspect of the standard was considered and approved by committee ballot(s). The accumulation of
these ballots was then incorporated to prepare the LPDDR4 standard.

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JEDEC JESD79-4-1

Addendum No. 1 to JESD79-4, 3D Stacked DRAM Standard

Published by: 2017-02-01 / 2017-02-01 / 64 pages
This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58C

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JEDEC JESD82-31

DDR4 REGISTER CLOCK DRIVER (DDR4RCD01)

Published by: 2016-08-01 / 2016-08-01 / 150 pages
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR4 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR4 RDIMM and LRDIMM applications. Any TBDs as of this document, are under discussion by the formulating committee.

The terms ‘Registering Clock Driver’, ‘RCD’, ‘register’ or ‘device’ are used interchangeably to refer to this device in the remainder of this specification.

The purpose is to provide a standard for the DDR4RCD01 (see Note) logic device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

NOTE The designation DDR4RCD01 refers to the part designation of a series of commercial logic parts common in the industry. This designation is normally preceded by a series of manufacturer specific characters to make up a complete part designation.

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JEDEC JESD245A

Byte Addressable Energy Backed Interface

Published by: 2016-09-01 / 2016-09-01 / 118 pages
The purpose of this standard is definition of an energy backed byte addressable function on a nonvolatile dual in-line memory module (NVDIMM). This standard defines the feature set and commands implemented by the energy backed byte addressable function on the NVDIMM.

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JEDEC JESD248

DDR4 NVDIMM-N Design Standard

Published by: 2016-09-01 / 2016-09-01 / 47 pages
This standard defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Double Data Rate, Synchronous SDRAM Nonvolatile Dual In-Line Memory Modules with NAND Flash backup (DDR4 NVDIMM-N). A DDR4 NVDIMM-N is a Hybrid Memory Module with a DDR4 DIMM interface consisting of DRAM that is made nonvolatile through the use of NAND Flash. NVDIMM-N modules adhere to the Byte Addressable Energy Backed Interface Standard, JESD245, that provides detailed logical behavior, interface, and register definitions. These DDR4 NVDIMM-N modules are intended for use as main memory or storage when installed in PCs. Item 2233.27

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JEDEC JEP174

UNDERSTANDING ELECTRICAL OVERSTRESS – EOS

Published by: 2016-09-01 / 2016-09-01 / 174 pages
The purpose of this white paper will be to introduce a new perspective about EOS to the electronics industry. As failures exhibiting EOS damage are commonly experienced in the industry, and these severe overstress events are a factor in the damage of many products, the intent of the white paper is to clarify what EOS really is and how it can be mitigated once it is properly comprehended.

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JEDEC JESD232AA

Graphics Double Data Rate (GDDR5X) SGRAM Standard

Published by: 2016-08-01 / 2016-08-01 / 160 pages
This document defines the GDDR5X SGRAM memory standard, including features, device operation,
electrical charactersitics, timings, signal pin assignments and package.

The purpose of this standard is to define the minimum set of requirements for JEDEC standard compatible
4 Gb through 16 Gb x32 GDDR5X SGRAM devices. System designs based on the required aspects of this
standard will be supported by all GDDR5X SGRAM vendors providing JEDEC standard compatible
devices. Some aspects of the GDDR5X standard such as AC timings were not standardized. Some features
are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted
for specifics.

This standard was created based on the GDDR5 SGRAM standard (JESD212). Each aspect of the changes
were considered and balloted. The accumulation of these ballots were then incorporated to prepare this
GDDR5X SGRAM standard.

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JEDEC JS709B

Joint JEDEC/ECA Standard: Definition of "Low-Halogen" for Electronic Products

Published by: JEDEC Solid State Technology Association / 2015-04-01 / 18 pages
This standard provides terms and definitions for “low-halogen” electronic products that have the potential to contain the halogens Br and Cl from the use of BFRs, CFRs, and PVC, and recommends methods for marking and labeling.

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