HIGH BANDWIDTH MEMORY (HBM) DRAM
Published by: JEDEC Solid State Technology Association / 10/01/2013 / 124 pages
The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 28b data bus operating at DDR data rates.